Improving processor efficiency by statically pipelining instructions
نویسندگان
چکیده
منابع مشابه
Improving Software Pipelining by Hiding Memory Latency
Modern processors and compilers hide long memory latencies through non-blocking loads or explicit software prefetching instructions. Unfortunately , each mechanism has potential drawbacks. Non-blocking loads can signiicantly increase register pressure by extending the lifetimes of loads. Software prefetching increases the number of memory instructions in the loop body. For a loop whose executio...
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ژورنال
عنوان ژورنال: ACM SIGPLAN Notices
سال: 2013
ISSN: 0362-1340,1558-1160
DOI: 10.1145/2499369.2465559